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Five-Year Integrated Master's Programme (FYIMP) in Microelectronics & Semiconductor

Five-Year Integrated Master's Programme (FYIMP)Check with your papers

CUET papers this programme asks for

From the institution's own document, page 2

A candidate qualifies when every non-optional line is satisfied.

Combination 1
  • Physicsdomain

Choose your papers once and every line here is marked against them. Choose papers

The mapping maps this programme to Physics alone. Admission requires a Senior Secondary (10+2) or equivalent pass with Physics and Mathematics from any Board.

Cut-offs, 2024–2026

2025 · Not publishedBirangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam published no programme-wise cut-off for 2025. Check here instead: Birangana Sati Sadhani Rajyik Vishwavidyalaya UG admissions 2025 — Samarth-portal merit; no CUET cut-off published
2024 · Not publishedBirangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam published no programme-wise cut-off for 2024. Check here instead: Birangana Sati Sadhani Rajyik Vishwavidyalaya UG admissions 2024 — Samarth-portal merit; no CUET cut-off published

One row per college or variant, highest first. Each links to the list it was copied from.

FigureURSource
Closing score
last admitted, from merit list
63.03p. 1

Showing 1 of 1 published lines for Round 1, 2026. A dot means no seat was allocated in that category in that round; “not printed” means the list shows the cell but no number.

All Birangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam CUET cut-offs, programme by programme

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Questions

Which CUET papers does Five-Year Integrated Master's Programme (FYIMP) in Microelectronics & Semiconductor at Birangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam require?
Physics. The rule is taken from Birangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam's own CUET (UG) 2026 course-mapping document, page 2, and was last verified on 2026-09-15.
Which CUET subjects can be used to apply for Five-Year Integrated Master's Programme (FYIMP) in Microelectronics & Semiconductor at Birangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam?
Physics. Each of these papers appears in the programme's mapped rule.
What is the latest CUET cut-off for Five-Year Integrated Master's Programme (FYIMP) in Microelectronics & Semiconductor at Birangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam?
The last closing score on record is 63.03, for the unreserved category in 2026, from Birangana Sati Sadhani Rajyik Vishwavidyalaya, Golaghat, Assam's own allocation document.

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Domain subjects